Technical Field
Embodiments of the present invention relate to the field of display technologies, and particularly, to a pixel unit used in an array substrate of a display device and a method for manufacturing the same, an array substrate comprising the pixel unit, and a display device and a method for manufacturing the same. Embodiments of the present invention are specifically suitable to these pixel units, array substrates and display devices including a thin-film transistor (TFT) which comprises an active layer made of oxide.
Description of the Related Art
Organic Light-Emitting Diode (OLED) has advantages of active luminescence, high luminescent efficiency, fast response time (at a magnitude of 1 μs), low working voltage (of 3˜10V), wide viewing angle (of greater than 170°), thin panel thickness (of less than 2 mm), low power consumption, broad working temperature range (of −4° C.˜85° C.), flexible displaying and the likes. Accordingly, it becomes a third generation display technology after CRT and LCD.
Production processes such as small molecule evaporation, polymer spin coating, inkjet printing, large-area printing may be adopted in the manufacture of OLED, which have relatively low manufacturing cost and are suitable to mass production. This makes OLED more and more competitive with fluorescent lamps in the long run. Relative to point light source of LED, White Organic Light-Emitting Diode (WOLED), belonging to surface light source, can be used to manufacture flat plate light source and is more suitable for backlight source of liquid crystal display device and full color OLED display device. WOLED has great potential on application of flat plate lightings, accordingly, WOLED becomes hot topic of development over the past 10 years and is expected to be a leading role in new generation semiconductor lighting as the LED does.
Nowadays, in order to achieve manufacture of OLED array substrate with large-scale in area and high in resolution ratio, bottom-gate 7-Mask (7 times of patterning, that is, the mask is used 7 times) process is used in prior art.
FIGS. 1A and 1B show flow diagrams of a conventional method for manufacturing a bottom-gate type thin-film transistor of an OLED array substrate, in which FIG. 1A shows former four patterning processes and FIG. 1B shows later three patterning processes.
Each pixel unit used in the OLED array substrate comprises two thin-film transistors (i.e., Switching TFT and Driving TFT), and a drain of the switching TFT is electrically connected with a gate of the driving TFT.
Referring to FIG. 1A, the abovementioned processes comprise the following steps.
Step S11 of forming a gate 102 of a switching TFT and a gate 102′ of a driving TFT on a substrate 101, and depositing a Gate Insulating Layer (FIL) 103 over the gate 102 of the switching TFT and the gate 102′ of the driving TFT.
Procedure of forming the gate 102 of the switching TFT and the gate 102′ of the driving TFT comprises: forming a gate layer thin film, and forming a pattern including the gate 102 and the gate 102′ by means of one patterning process (1st Mask).
Step S12 of forming an active layer 104 over the gate insulating layer 103.
Material for the active layer can be Indium Gallium Zinc Oxide (IGZO). Procedure of forming the active layer 104 comprises: forming an active layer thin film, and, forming a pattern including the acting layer by means of one patterning process (2nd Mask).
Step S13 of forming an Etch Stop Layer (ESL) 105 over the active layer 104.
Procedure of forming the etch stop layer 105 over the active layer 104 comprises: forming a pattern including the etch stop layer 105 by means of one patterning process (3rd Mask).
Step S14 of forming an opening, for connection between a gate 102′ of the driving TFT and a drain of a switching TFT to be formed later, on the gate insulating layer 103 above the gate of the driving TFT.
Procedure of forming the opening comprises: forming a gate insulating layer pattern including the opening by means of one patterning process (4th Mask).
Referring to FIG. 1B, next is step S15 of forming a source 1061 and a drain 1062 on the substrate after the preceding steps.
Procedure of forming the source 1061 and the drain 1062 comprises: forming a source-drain thin film, and, forming a pattern including the source 1061 and the drain 1062 by means of one patterning process (5th Mask).
Step S16 of depositing a protective layer (PVX or passivation layer) 107, and forming an opening, for connection between a gate 102′ of the driving TFT and a drain 1062 of the switching TFT, on the protective layer 107 above the drain 1062 of the switching TFT and the gate of the driving TFT.
Procedure of forming the opening comprises: forming a protective layer pattern including the opening by means of one patterning process (6th Mask).
Step S17 of forming a conductive pattern 108 over the protective layer 107. Material for the conductive pattern can be Indium Tin Oxide (ITO).
Procedure of forming the conductive pattern 108 comprises: forming a transparent conductive film thin film, and, forming a pattern including the conductive pattern 108 by means of one patterning process (7th Mask).
Concerning the above manufacturing method, the manufacture of TFT requires 7 times of patterning processes (7-mask), which is complicated in process flow.
Nowadays, Active Matrix Organic Light Emitting Diode (AMOLED) with large-scale size, high resolution ratio, high refresh rate and 3D form is considered as a trend of future development. It employs low-resistivity wiring technology and high mobility TFT. Cu+Oxide (Copper Gate and Oxide Active Layer) technology is very competitive if it fulfills above mentioned requirements. However, Cu itself has very high diffusion coefficient, and, Cu element will diffuse towards the active layer during use of the TFT, which deteriorates semiconductor performance of the TFT and increases the drain current.